View XRT91L800507_1229264.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xr xr xr preliminary xrt91l80 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r july 2005 rev. p1.1.0 general description the xrt91l80 is a fully integrated sonet/sdh transceiver for sonet oc-48/stm-16 applications supporting the use of forward error correction (fec ) capability. the transceiver includes an on-chip clo ck multiplier unit (cmu), which uses a high frequency phase-locked loop (pll) to generate the high- speed transmit serial clock from a slower external clock reference. it also provides clock and data recovery (cdr) functions by synchronizing its on- chip voltage controlled oscillator (vco) to the incoming serial data stream. the chip provides seri al- to-parallel and parallel-to-serial converters and 4 -bit lvds system interfaces in both receive and transmit directions. the transmit section includes a 4x9 ela stic buffer (fifo) to absorb any phase differences between the transmitter clock input and the interna lly generated transmitter reference clock. in the event of an overflow, an internal fifo control circuit outpu ts an overflow indication. the fifo under the control of the fifo_autorst pin can automatically recover from an overflow condition. the operation o f the device can be monitored by checking the status of the lockdet_cmu, lockdet_cdr, and losdet output signals. an on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering pll with an external vcxo that can be used in loop timing mode to clean up the recovered clock in the receive section. applications sonet/sdh-based transmission systems add/drop multiplexers cross connect equipment atm and multi-service switches and routers dslams sonet/sdh test equipment dwdm termination equipment f igure 1. b lock d iagram of xrt91l80 piso (parallel input serial output) pfd & charge pump txdi0p/n sclk sdi serial microprocessor hardware control int sdo reset host/hw rloops dloop rloopp looptm_ja looptm_noja txdi1p/n txdi2p/n txdi3p/n txpclkip/n dloop rloopp rxdo0p/n rxdo1p/n rxdo2p/n rxdo3p/n 4x9 fifo wp rp rloops cdr re-timer cmu txop/n rxip/n refclkp/n vcxo_inp/n altfreqsel vcxo_sel vcxo_locken vcxo_lock cpout loopbw txpclkop/n txclko16p/n txclko16dis lockdet_cmu overflow fifo_rst fifo_autorst losdmute lockdet_cdr losdet sdext polarity disrd sts-48 transceiver cs test jtag tdo tdi tck tms trst div by 4 div by 16 rxpclkop/n rxclko16p/n div by 4 div by 16 sipo (serial input parallel output)
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 2 features 2.488 / 2.666 gbps transceiver targeted for sonet oc-48/sdh stm-16 applications selectable full duplex operation between standard r ate of 2.488 gbps or forward error correction rate of 2.666 gbps single-chip fully integrated solution containing pa rallel-to-serial converter, clock multiplier unit ( cmu), serial- to-parallel converter, and clock data recovery (cdr ) functions 4-bit lvds signaling data paths running at 622.08/6 66.51 mbps compliant with oif sfi-4 implimentation agreement non-fec and fec rate refclkp/n single reference inp ut port supports 77.76/83.31 mhz or 155.52/166.63 mhz trans mit and receive external reference input port optional vcxo input port support multiple de-jitter ing modes on-chip phase detector and charge pump for external vcxo based de-jittering pll internal fifo decouples transmit parallel clock inp ut and transmit parallel clock output provides local, remote serial, remote parallel and split loopback modes as well as loop timing mode diagnostics features include various lock detect fu nctions and transmit cmu and receive cdr lock detec t host mode serial microprocessor interface simplifie s monitor and control meets telcordia, ansi and itu-t jitter requirements including t1.105.03 - 2002 sonet jitter tolerance specification, gr-253 core, gr-253 ilr sonet jitter specifications. operates at 1.8v cmos and cml with 3.3v i/o 490mw typical power dissipation package: 12 x 12 mm 196-pin stbga ieee 1149.1 compatable jtag port product ordering information p roduct n umber p ackage t ype o perating t emperature r ange xrt91l80ib 196 stbga -40c to +85c
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 3 f igure 2. 196 bga p inout of the xrt91l80 (t op v iew ) rxdo3p rxdo3n rxdo1p rxdo1n rxpclkop rxpclkon dgnd txpclkip txpclkin txdi1p txdi1n txdi3p txdi3n vdd3.3 14 vdd1.8 vdd1.8 rxdo2p rxdo2n rxdo0p rxdo0n dgnd txdi0p txdi0n txdi2p txdi2n overflow fifo_rst vdd3.3 13 dgnd dgnd disrd vdd1.8 vdd1.8 dgnd dgnd dgnd dgnd dgnd dgnd txclko16dis fifo_autorst dgnd 12 rloopp tdo int vdd3.3 vdd3.3 dgnd dgnd dgnd dgnd vdd1.8 dgnd vdd1.8 txclko16n txpclkon 11 cs reset rloops vdd3.3 tgnd tgnd tgnd tgnd tgnd tgnd vdd1.8 vdd1.8 txclko16p txpclkop 10 sdi sclk host/hw vdd3.3 tgnd tgnd tgnd tgnd tgnd tgnd vdd1.8 vdd1.8 avdd1.8_tx avdd3.3_tx 9 vdd3.3 dgnd sdo avdd1.8_rx tgnd tgnd tgnd tgnd tgnd tgnd avdd1.8_tx tdi vcxo_lock cpout 8 rxclko16n vdd1.8 lockdet_cdr agnd_rx tgnd tgnd tgnd tgnd tgnd tgnd avdd1.8_tx loopbw agnd_tx agnd_tx 7 rxclko16p dloop looptm_ja avdd1.8_rx tgnd tgnd tgnd tgnd tgnd tgnd avdd1.8_tx vcxo_sel refclkn refclkp 6 dgnd sdext losdet avdd1.8_rx tgnd tgnd tgnd tgnd tgnd tgnd agnd_tx agnd_tx agnd_tx avdd3.3_tx 5 nc nc polarity avdd1.8_rx agnd_rx agnd_rx agnd_rx agnd_rx avdd1.8_tx agnd_tx agnd_tx agnd_tx vcxo_inn vcxo_inp 4 losdmute dgnd agnd_rx avdd3.3_rx avdd3.3_rx avdd1.8_rx avdd1.8_rx agnd_rx agnd_tx agnd_tx dgnd avdd1.8_tx tck vcxo_locken 3 trst agnd_rx agnd_rx agnd_rx agnd_rx agnd_rx agnd_rx agnd_rx agnd_tx agnd_tx agnd_tx avdd1.8_tx lockdet_cmu looptm_noja 2 agnd_rx agnd_rx rxip rxin agnd_rx xres1n xres1p agnd_rx avdd1.8_tx txop txon agnd_tx tms altfreqsel 1 ab cd e f g h j k l m n p
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 i table of contents general description ................................ ................................................... ..............1 applications ....................................... ................................................... .................................................1 f igure 1. b lock d iagram of xrt91l80 .......................................... ................................................... ......................................... 1 features ................................................... ................................................... ................................................2 product ordering information ....................... ................................................... ........................2 f igure 2. 196 bga p inout of the xrt91l80 (t op v iew ).................................................. ................................................... ..... 3 t able of c ontents .................................................. ................................................... ....... i pin descriptions ................................... ................................................... ....................4 s erial m icroprocessor interface ................................................... ................................................... ......4 h ardware common control ................................................... ................................................... ................5 t ransmitter s ection ................................................... ................................................... ............................6 receiver section ................................................... ................................................... ...................................9 p ower and g round ................................................... ................................................... ............................10 n o c onnects ................................................... ................................................... .......................................11 jtag ............................................... ................................................... ................................................... .....12 1.0 functional description ...................... ................................................... ....................................13 1.1 hardware mode vs. host mode ................. ................................................... ...................................... 13 1.2 clock input reference ....................... ................................................... ............................................... 13 t able 1: r eference f requency o ptions (n on -fec and fec m ode ).................................................. .................................... 13 1.3 forward error correction (fec) .............. ................................................... ................................... 13 f igure 3. s implified b lock d iagram of f orward e rror c orrection ................................................... ................................. 13 2.0 receive section ............................. ................................................... .............................................14 2.1 receive serial input ........................ ................................................... ................................................... . 14 f igure 4. r eceive s erial i nput i nterface b lock ................................................... ................................................... ............... 14 t able 2: d ifferential cml i nput s wing p arameters ................................................... ................................................... ........ 14 2.2 receive clock and data recovery ............. ................................................... .................................. 15 t able 3: c lock and d ata r ecovery u nit p erformance ................................................... ................................................... .... 15 2.3 external signal detection ................... ................................................... ........................................... 15 t able 4: losd d eclaration p olarity s etting ................................................... ................................................... ................... 16 2.4 receive serial input to parallel output (sipo ) ................................................. ........................ 16 f igure 5. s implified b lock d iagram of sipo .............................................. ................................................... .......................... 16 2.5 receive parallel output interface ........... ................................................... ................................. 16 f igure 6. r eceive p arallel o utput i nterface b lock ................................................... ................................................... ....... 16 2.6 receive parallel interface lvds operation ... ................................................... ........................ 17 f igure 7. lvds external biasing resistors ................................................... ................................................... ....................... 17 2.7 parallel receive data output mute upon losd . ................................................... .................... 17 2.8 parallel receive data output disable ........ ................................................... .............................. 17 2.9 receive parallel data output timing ......... ................................................... ................................ 17 f igure 8. r eceive p arallel o utput t iming ................................................... ................................................... ........................ 17 t able 5: r eceive p arallel d ata and c lock o utput t iming s pecifications ................................................... ........................ 17 3.0 transmit section ............................ ................................................... ...........................................18 3.1 transmit parallel input interface ........... ................................................... ................................... 18 f igure 9. t ransmit p arallel i nput i nterface b lock ................................................... ................................................... ......... 18 3.2 transmit parallel data input timing ......... ................................................... .................................. 19 f igure 10. t ransmit p arallel i nput t iming ................................................... ................................................... ........................ 19 t able 6: t ransmit p arallel d ata and c lock i nput t iming s pecification ................................................... ............................ 19 t able 7: t ransmit p arallel c lock o utput t iming s pecification ................................................... ........................................ 19 3.3 transmit fifo ............................... ................................................... ................................................... ........ 19 f igure 11. t ransmit fifo and s ystem i nterface ................................................... ................................................... .............. 20 3.4 fifo calibration upon power up .............. ................................................... ...................................... 20 3.5 transmit parallel input to serial output (pis o) ................................................ ...................... 20 f igure 12. s implified b lock d iagram of piso .............................................. ................................................... ........................ 20 3.6 clock multiplier unit (cmu) and re-timer .... ................................................... .............................. 21 t able 8: c lock m ultiplier u nit p erformance ................................................... ................................................... ................... 21 3.7 loop timing and clock control ............... ................................................... ...................................... 21 t able 9: l oop timing and reference de - jitter configurations ................................................... ........................................... 22 f igure 13. l oop t iming m ode u sing an e xternal c leanup vcxo.............................................. ............................................ 22 3.8 external loop filter ........................ ................................................... .................................................. 23
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r ii f igure 14. s implified d iagram of the e xternal l oop f ilter ................................................... ............................................... 23 3.9 transmit serial output control .............. ................................................... .................................... 23 f igure 15. t ransmit s erial o utput i nterface block ................................................... ................................................... ........ 23 4.0 diagnostic features ......................... ................................................... ....................................... 24 4.1 serial remote loopback ...................... ................................................... ............................................ 24 f igure 16. s erial r emote l oopback ................................................... ................................................... ................................... 24 4.2 parallel remote loopback .................... ................................................... ........................................ 24 f igure 17. p arallel r emote l oopback ................................................... ................................................... .............................. 24 4.3 digital local loopback ...................... ................................................... .............................................. 25 f igure 18. d igital l oopback ................................................... ................................................... ................................................ 25 4.4 sonet jitter requirements ................... ................................................... ........................................... 26 4.4.1 jitter tolerance: .......................... ................................................... ................................................... ................ 26 f igure 19. j itter t olerance m ask ................................................... ................................................... ...................................... 26 f igure 20. 91l80 m easured jitter tolerance with external jitter attenuation enabled in looptiming at 2.488 g bps in sts- 48................................................. ................................................... ................................................... ........................... 27 4.4.2 jitter transfer ............................ ................................................... ................................................... .................. 27 f igure 21. 91l80 m easured jitter transfer with external jitter attenuation enabled in looptiming at 2.488 g bps in sts- 48................................................. ................................................... ................................................... ........................... 27 4.4.3 jitter generation.......................... ................................................... ................................................... ................ 28 f igure 22. 91l80 m easured e lectrical p hase n oise t ransmit j itter g eneration at 2.488 g bps ...................................... 28 f igure 23. 91l80 m easured e lectrical p hase n oise r eceive j itter g eneration at 2.488 g bps ........................................ 28 5.0 serial microprocessor interface block ....... ................................................... ............... 29 f igure 24. s implified b lock d iagram of the s erial m icroprocessor i nterface ................................................... .............. 29 5.1 serial timing information ................... ................................................... ............................................. 29 f igure 25. t iming d iagram for the s erial m icroprocessor i nterface ................................................... ............................. 29 5.2 16-bit serial data input descritption ....... ................................................... ................................... 30 5.2.1 r/w (sclk1)................................ ................................................... ................................................... ......................... 30 5.2.2 a[5:0] (sclk2 - sclk7)..................... ................................................... ................................................... .................. 30 5.2.3 x (dummy bit sclk8) ........................ ................................................... ................................................... ................ 30 5.2.4 d[7:0] (sclk9 - sclk16).................... ................................................... ................................................... ................. 30 5.3 8-bit serial data output description ........ ................................................... .................................. 30 6.0 register map and bit descriptions ........... ................................................... ......................... 31 t able 10: m icroprocessor r egister m ap ................................................... ................................................... .......................... 31 t able 11: m icroprocessor r egister 0 x 00 h b it d escription ................................................... .............................................. 31 t able 12: m icroprocessor r egister 0 x 01 h b it d escription ................................................... .............................................. 32 t able 13: m icroprocessor r egister 0 x 02 h b it d escription ................................................... .............................................. 32 t able 14: m icroprocessor r egister 0 x 03 h b it d escription ................................................... .............................................. 33 t able 15: m icroprocessor r egister 0 x 04 h b it d escription ................................................... .............................................. 35 t able 16: m icroprocessor r egister 0 x 05 h b it d escription ................................................... .............................................. 35 t able 17: m icroprocessor r egister 0 x 3e h b it d escription ................................................... .............................................. 37 t able 18: m icroprocessor r egister 0 x 3f h b it d escription ................................................... .............................................. 37 7.0 electrical characteristics .................. ................................................... .............................. 38 a bsolute m aximum ratings ........................................... ................................................... .................... 38 power and current dc e lectrical c haracteristics ................................................... ................. 38 ................................................... ................................................... ................................................... .......... 39 c ommon mode logic signal dc electrical characteristics ........ ........................................ 39 ................................................... ................................................... ................................................... .......... 39 lvpecl logic signal dc electrical characteristics .. ................................................... ..... 39 lvds logic signal dc electrical characteristics.... ................................................... ........ 40 lvttl/lvcmos s ignal dc electrical characteristics ..................... ...................................... 40 ordering information ............................... ................................................... ................................ 41 r evision h istory ................................................... ................................................... ................................ 42
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 4 pin descriptions serial microprocessor interface n ame l evel t ype p in d escription host/hw lvttl, lvcmos i c9 host or hardware mode select input the xrt91l80 offers two modes of operation for inte rfacing to the device. the host mode uses a serial microprocessor interface for programming individual registers. the hardware mode is controlled by the state of the hardware pins set by the user. when left uncon- nected, by default, the device is configured in the hardware mode. "low" = hardware mode "high" = host mode this pin is provided with an internal pull-down. cs lvttl, lvcmos i a10 chip select input (host mode only) active "low" signal. this signal enables the seria l microprocessor interface by pulling chip select "low". the serial microprocessor is disabled when the chip select signal returns "high" . n ote : the serial microprocessor interface does not support burst mode. chip select must be de-asserted after each operation cycle. this pin is provided with an internal pull-up. sclk lvttl, lvcmos i b9 serial clock input (host mode only) once cs is pulled "low", the serial microprocessor interfa ce requires 16 clock cycles for a complete read or wri te operation. this pin is provided with an internal pull-down. sdi lvttl, lvcmos i a9 serial data input (host mode only) when cs is pulled "low", the serial data input is sampled on the ris- ing edge of sclk. this pin is provided with an internal pull-down. sdo lvcmos o c8 serial data output (host mode only) if a read function is initiated, the serial data ou tput is updated on the falling edge of sclk8 through sclk15, with the lsb (d0) updated first. this enables the data to be sampled on the rising edge of sclk9 through sclk16. int lvcmos o c11 interrupt output (host mode only) active "low" signal. this signal is asserted "low" when a change in alarm status occurs. once the status registers hav e been read, the interrupt pin will return "high". n ote : this pin requires an external pull-up resistor. reset lvttl, lvcmos i b10 master reset input active "low" signal. when this pin is pulled "low" for more than 10 m s, the internal registers are set to their default state. see the register description for the default values. this pin is provided with an internal pull-up.
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 5 hardware common control n ame l evel t ype p in d escription rloops lvttl, lvcmos i c10 serial remote loopback the serial remote loopback mode interconnects the r eceive serial data input to the transmit serial data outpu t. if serial remote loopback is enabled, the 4-bit parallel tran smit data input is ignored while the 4-bit parallel receive d ata output is maintained. "low" = disabled "high" = serial remote loopback mode enabled n ote : dloop and rloops can be enabled simultaneously to achieve a dual loopback diagnostic feature. this pin is provided with an internal pull-down. rloopp lvttl, lvcmos i a11 parallel remote loopback the parallel remote loopback mode allows the serial data input stream to pass through the clock and data recovery circuit and looped-back at the parallel interface to the serial output port. the 4-bit parallel transmit data input is ignored w hile the 4-bit parallel receive data output is maintained. "low" = disabled "high" = parallel remote loopback mode enabled n ote : dloop and rloops should be disabled when rloopp is enabled. the internal fifo should also be flushed using fifo_rst pin or register bit when parallel remote loopback is enabled/disabled. this pin is provided with an internal pull-down. dloop lvttl, lvcmos i b6 digital local loopback the digital local loopback mode interconnects the 4 -bit parallel transmit data and parallel transmit clock input to the 4-bit paral- lel receive data and parallel receive clock output respectively while maintaining the transmit serial data output. if digital local loopback is enabled, the receive serial data input is ignored. "low" = disabled "high" = digital local loopback mode enabled n ote : dloop and rloops can be enabled simultaneously to achieve a dual loopback diagnostic feature. this pin is provided with an internal pull-down.
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 6 looptm_ja lvttl, lvcmos i c6 loop timing mode with jitter attenuation the looptm_ja pin must be set "high" in order to se lect the recovered receive clock as the reference source for the de-jitter pll. "low" = disabled "high" = loop timing with de-jitter pll activated this pin is provided with an internal pull-down. looptm_noja lvttl, lvcmos i p2 loop timing mode with no jitter attenuation when the loop timing mode is activated, the externa l local refer- ence clock input to the cmu is replaced with the 1/ 16th or 1/ 32nd of the high-speed recovered receive clock comi ng from the cdr. "low" = disabled "high" = loop timing activated this pin is provided with an internal pull-down. transmitter section n ame l evel t ype p in d escription txdi0p txdi0n txdi1p txdi1n txdi2p txdi2n txdi3p txdi3n lvds i h13 j13 k14 l14 k13 l13 m14 n14 transmit parallel data input the 622.08 mbps 4-bit parallel transmit data input should be applied to the transmit parallel bus simultaneously to be sam- pled at the rising edge of the txpclkip/n input. t he 4-bit par- allel interface is multiplexed into the transmit se rial output interface msb first (txdi3p/n). n ote : the xrt91l80 can accept 666.51 mbps 4-bit parallel transmit data input for forward error correction (f ec) applications. txpclkip txpclkin lvds i h14 j14 transmit parallel clock input 622.08 mhz clock input used to sample the 4-bit par allel trans- mit data input txdi[3:0]p/n. n ote : the xrt91l80 can accept a 666.51 mhz transmit clock input for forward error correction (fec) applicatio ns. txop txon cmldiff o k1 l1 transmit serial data output the transmit serial data output stream is generated by multi- plexing the 4-bit parallel transmit data input into a 2.488 gbps serial data output stream. in forward error correc tion, the transmit serial data output stream is 2.666 gbps. refclkp refclkn lvpecl i p6 n6 reference clock input this differential clock input reference is used for the transmit clock multiplier unit (cmu) to provide the necessar y high-speed clock reference for this device. pin altfreqsel de termines the value used as the reference. see pin altfreqse l for more details. vcxo_inp vcxo_inn lvpecl i p4 n4 voltage controled oscillator input this differential clock input is used for the trans mit pll jitter attenuation. pin altfreqsel determines the value u sed as the reference. see pin altfreqsel for more details . hardware common control n ame l evel t ype p in d escription
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 7 altfreqsel lvttl, lvcmos i p1 reference clock frequency select this pin is used to select the frequency of the ref clkp/n clock input to the cmu. "low" = 77.76 mhz (83.31 mhz for fec) "high" = 155.52 mhz (166.63 mhz for fec) this pin is provided with an internal pull-up. vcxo_sel lvttl, lvcmos i m6 de-jitter vcxo select option this pin selects either the normal refclkp/n or the de-jitter vcxo_inp/n pin as a reference clock to the cmu. "low" = normal refclkp/n reference clock "high" = de-jitter vcxo_inp/n reference clock this pin is provided with an internal pull-down. vcxo_lock lvcmos o n8 de-jitter pll lock detect if the de-jitter pll lock detect is enabled with pi n p3 and the de- jitter vcxo mode is selected by pin m6, this pin wi ll assert "high" when the pll is locked. "low" = vcxo out of lock "high" = vcxo locked vcxo_locken lvttl, lvcmos i p3 de-jitter pll lock detect enable this pin enables the vcxo_inp/n lock detect circuit and vcxo_lock pin n8 to be active. "low" = vcxo lock detect disabled "high" = vcxo lock detect enabled this pin is provided with an internal pull-down. cpout - o p8 charge pump output (for external vcxo) the nominal output of the charge pump current is 25 0 m a loopbw lvttl, lvcmos i m7 cmu loop bandwidth select this pin is used to select the bandwidth of the clo ck multiplier unit of the transmit path to a narrow or wide band. use wide band for clean reference signals and narrow band fo r noisy ref- erences. "low" = wide band (4x) "high" = narrow band (1x) this pin is provided with an internal pull-down. txpclkop txpclkon lvds o p10 p11 transmit parallel clock output this 622.08 mhz clock can be used for the downstrea m device to generate the txdi[3:0]p/n data and txpclkip/n cl ock input. this enables the downstream device and the s ts-48/ stm-16 transceiver to be in synchronization. n ote : the xrt91l80 can output a 666.51 mhz transmit clock output for forward error correction (fec). transmitter section n ame l evel t ype p in d escription
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 8 txclko16p txclko16n lvds o n10 n11 auxiliary clock output (155.52/166.63 mhz) 155.52/166.63 mhz auxiliary clock derived from cmu output. this clock can also be used for the downstream devi ce as a ref- erence for generating the txdi[3:0]p/n data and txp clkip/n clock input. this enables the downstream device and the sts- 48/stm-16 transceiver to be in synchronization. the output of this pin is controlled by txclko16dis. txclko16dis lvttl, lvcmos i m12 auxiliary clock disable this pin is used to control the activity of the aux iliary clock. "low" = txclko16p/n enabled "high" = txclko16p/n disabled this pin is provided with an internal pull-down. lockdet_cmu lvcmos o n2 cmu lock detect this pin is used to monitor the lock condition of t he clock multi- plier unit. "low" = cmu out of lock "high" = cmu locked overflow lvcmos o m13 transmit fifo overflow this pin is used to monitor the transmit fifo statu s. "low" = normal status "high" = overflow condition fifo_rst lvttl, lvcmos i n13 fifo control reset fifo_rst should be held "high" for a minimum of 2 t xp- clkop/n cycles after powering up and during manual fifo reset. after the fifo_rst pin is returned "low," i t will take 8 to 10 txpclkop/n cycles for the fifo to flush out. upo n an interrupt indication that the fifo has an overflow condition, this pin is used to reset or flush out the fifo. "low" = normal operation "high" = manual fifo reset n ote : to automatically reset the fifo, see fifo_autorst pin. this pin is provided with an internal pull-down. fifo_autorst lvttl, lvcmos i n12 automatic fifo overflow reset if this pin is set "high", the sts-48/stm-16 transc eiver will automatically flush the fifo upon an overflow condi tion. upon power-up, the fifo should be manually reset by sett ing fifo_rst "high" for a minimum of 2 txpclkop/n cycle s. "low" = manual fifo reset required for overflow con ditions "high" = automatically resets fifo upon overflow de tection this pin is provided with an internal pull-down. transmitter section n ame l evel t ype p in d escription
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 9 receiver section n ame l evel t ype p in d escription rxdo0p rxdo0n rxdo1p rxdo1n rxdo2p rxdo2n rxdo3p rxdo3n lvds o e13 f13 c14 d14 c13 d13 a14 b14 receive parallel data output 622mbps 4-bit parallel receive data output is updat ed simulta- neously on the rising edge of the rxpclkop/n output . the 4- bit parallel interface is de-multiplexed from the r eceive serial data input msb first (rxdo3p/n). n ote : the xrt91l80 can output 666.51 mbps 4-bit parallel receive data output for forward error correction (f ec) applications. rxpclkop rxpclkon lvds o e14 f14 receive parallel clock output 622.08 mhz parallel clock output used to update the 4-bit paral- lel receive data output rxdo[3:0]p/n at the rising edge of this clock.. n ote : the xrt91l80 can output a 666.51 mhz receive clock output for forward error correction (fec). disrd lvttl lvcmos i c12 parallel receive data output disable this pin is used to disable the rxdo[3:0]p/n parall el receive data output bus asynchronously. "low" = normal mode "high" = forces rxdo[3:0]p/n to a logic state "0" this pin is provided with an internal pull-down. rxip rxin cmldiff i c1 d1 receive serial data input the receive serial data stream of 2.488 gbps is app lied to these input pins. in forward error correction, th e receive serial data stream is 2.666 gbps. xres1p xres1n - i g1 f1 external lvds biasing resistors a 402 w resistor with +/-1% tolerance should be placed acr oss these 2 pins for proper biasing. rxclko16p rxclko16n lvds o a6 a7 auxiliary clock output (155.52/166.63 mhz) 155.52/166.63 mhz auxiliary clock derived from divi de-by-16 cdr recovered clock. lockdet_cdr lvcmos o c7 cdr lock detect this pin is used to monitor the lock condition of t he clock and data recovery unit. "low" = cdr out of lock "high" = cdr locked sdext lvttl, lvcmos i b5 signal detect input from optical module hardware mode when inactive, it will immediately declare a loss of signal detect (losd) condition and assert l osdet output pin and control the activity of the rxdo[3:0 ]p/n parallel data output based on losdmute pin setting. host mode in addition to asserting losdet output pin, it wi ll update the losd condition on the registers and cont rol the activity of the rxdo[3:0]p/n parallel data output b ased on losdmute register bit setting. "active" = normal operation "inactive" = losd condition (sdext detects signal a bsence) this pin is provided with an internal pull-down.
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 10 polarity lvttl, lvcmos i c4 polarity for sdext input controls the signal detect polarity convention of s dext. "low" = sdext is active "low." "high" = sdext is active "high." this pin is provided with an internal pull-down. losdet lvcmos o c5 los detect condition flags losd condition based on sdext signal coming f rom the optical module. "low" = no alarm "high" = a los condition is present losdmute lvttl, lvcmos i a3 parallel receive data output mute upon losd if this pin is asserted "high", the receive data ou tput will auto- matically be forced to a logic state of "0" when an losd condi- tion occurs. "low" = disabled "high" = mute rxdo[3:0]p/n data upon losd condition this pin is provided with an internal pull-down. power and ground n ame t ype p in d escription vdd3.3 pwr a8, d9, d10, d11, e11, p13, p14 cmos digital 3.3v i/o power supply vdd3.3 should be isolated from the analog power sup plies. for best results, use a ferrite bead along with an inte rnal power plane separation. the vdd3.3 power supply pins should ha ve bypass capacitors to the nearest ground. avdd3.3_rx pwr d3, e3 analog 3.3v i/o receiver power supply avdd3.3_rx should be isolated from the digital powe r supplies. for best results, use a ferrite bead along with an internal power plane separation. the avdd3.3_rx power supply pins should have bypass capacitors to the nearest ground. avdd3.3_tx pwr p5, p9 analog 3.3v i/o transmitter power supply avdd3.3_tx should be isolated from the digital powe r supplies. for best results, use a ferrite bead along with an internal power plane separation. the avdd3.3_tx power supply pins should have bypass capacitors to the nearest ground. vdd1.8 pwr a13, b7, b13, d12, e12, k11, l9, l10, m9, m10, m11 cmos digital 1.8v core power supply vdd1.8 should be isolated from the analog power sup plies. for best results, use a ferrite bead along with an inte rnal power plane separation. the vdd1.8 power supply pins should ha ve bypass capacitors to the nearest ground. avdd1.8_rx pwr d4, d5, d6, d8, f3, g3 analog 1.8v core receiver power supply avdd1.8_rx should be isolated from the digital powe r supplies. for best results, use a ferrite bead along with an internal power plane separation. the avdd1.8_rx power supply pins should have bypass capacitors to the nearest ground. receiver section n ame l evel t ype p in d escription
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 11 avdd1.8_tx pwr j1, j4, l6, l7, l8, m3, n9, m2 analog 1.8v core transmitter power supply avdd1.8_tx should be isolated from the digital powe r supplies. for best results, use a ferrite bead along with an internal power plane separation. the avdd1.8_tx power supply pins should have bypass capacitors to the nearest ground. dgnd gnd a5, a12, b3, b8, b12, f11, f12, g11, g12, g13, g14, h11, h12, j11, j12, k12, l3, l11, l12, p12 digital ground for 3.3v i/o and 1.8v core digital p ower supplies it is recommended that all ground pins of this devi ce be tied together. agnd_rx gnd a1, b1, b2, c2, c3, d2, d7, e1, e2, e4, f2, f4, g2, g4, h1, h2, h3, h4 receiver analog ground for 3.3v i/o and 1.8v core analog power supplies it is recommended that all ground pins of this devi ce be tied together. agnd_tx gnd j2, j3, k2, k3, k4, l2, l4, l5, m1, m4, m5, n5, n7, p7 transmitter analog ground for 3.3v i/o and 1.8v cor e analog power supplies it is recommended that all ground pins of this devi ce be tied together. tgnd gnd e5, e6, e7, e8, e9, e10, f5, f6, f7, f8, f9, f10, g5, g6, g7, g8, g9, g10, h5, h6, h7, h8, h9, h10, j5, j6, j7, j8, j9, j10, k5, k6, k7, k8, k9, k10 thermal ground it is recommended that all ground pins of this devi ce be tied together. no connects n ame l evel t ype p in d escription nc nc a4 b4 no connect this pin can be left floating or tied to ground. power and ground n ame t ype p in d escription
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 12 jtag s ignal n ame p in # t ype d escription tck n3 i test clock: boundary scan clock input. tms n1 i test mode select: boundary scan mode select input. jtag is disabled by default. note : this input pin should be pulled low for jtag op eration this pin is provided with an internal pull-up. tdi m8 i test data in: boundary scan test data input this pin is provided with an internal pull-up. tdo b11 o test data out: boundary scan test data output trst a2 i jtag test reset input note : this input pin should be pulled low to reset jt ag this pin is provided with an internal pull-up.
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 13 1.0 functional description the xrt91l80 transceiver is designed to operate wit h a sonet framer/asic device and provide a high- speed serial interface to optical networks. the tra nsceiver converts 4-bit parallel data at 622.08/666 .51 mbps to a serial cml bit stream at 2.488/2.666 gbps and vice-versa. it implements a clock multiplier unit ( cmu), sonet/sdh serialization/de-serialization (serdes), and receive clock and data recovery (cdr) unit. the transceiver is divided into transmit and receive se ctions and is used to provide the front end compone nt of sonet equipment, which includes primarily serial tr ansmit and receive functions. 1.1 hardware mode vs. host mode functionality of the sts-48/stm-16 transceiver can be configured by using either host mode or hardware mode. if hardware mode is selected by pulling host/ hw "low" or leaving this pin unconnected, the functionality is controlled by the hardware pins de scribed in the hardware pin descriptions. however, if host mode is selected by pulling host/hw "high", the functionality is controlled by program ming internal r/w registers using the serial microprocessor interface . whether using host or hardware mode, the function ality remains the same. therefore, the following sections describe the functionality rather than how each fu nction is controlled. the hardware pin descriptions and the r egister bit descriptions concentrate on configuring the device. 1.2 clock input reference the xrt91l80 can accept either a 77.76/83.3 mhz or 155.52/166.63 mhz clock input at refclkp/n as its internal timing reference for generating higher spe ed clocks. the reference clock can be provided with one of two frequencies chosen by altfreqsel. the reference frequency options for the xrt91l80 are listed in table 1. 1.3 forward error correction (fec) forward error correction is used to control errors along a one-way path of communication. fec sends ex tra information along with data which can be used by a receiver to check and correct the data without requ esting re-transmission of the original information. it doe s so by introducing a known structure into a data s equence prior to transmission. the most common methods are to replace a 14-bit data packet with a 15-bit codew ord structure, or to replace a 17-bit data packet with an 18-bit codeword structure. to maintain original bandwidth, a higher speed clock reference, derived by the rati o of 15/14 or 18/17 referenced to 77.76mhz or 155.5 2mhz is applied to the sts-48/stm-16 transceiver using a n external crystal. the xrt91l80 supports fec by accepting a clock input reference frequency of 83.3 1 mhz or 166.63 mhz. this allows the transmit 4-bit parallel data input to be applied to the sts-48/stm-16 trans ceiver at 666.51 mbps which is converted to a 2.666 gbps serial output stream to an optical module. a simpl ified block diagram of fec is shown in figure 3. t able 1: r eference f requency o ptions (n on -fec and fec m ode ) altfreqsel r eference c lock f requency t ransmit /r eceive d ata r ate o perating m ode 0 77.76/83.3 mhz 2.488/2.666 gbps sts-48/stm-16 1 155.52/166.63 mhz 2.488/2.666 gbps sts-48/stm-16 f igure 3. s implified b lock d iagram of f orward e rror c orrection sts-48 transceiver sonet/framer asic sonet/framer asic fec codec fec codec sts-48 transceiver optical module optical module optical fiber
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 14 2.0 receive section the receive section of xrt91l80 includes the differ ential inputs rxip/n, followed by the clock and dat a recovery unit (cdr) and receive serial-to-parallel converter (sipo). the receiver accepts the high spe ed non- return to zero (nrz) serial data at 2.488/2.666 gbp s through the differential input interfaces rxip/n. the clock and data recovery unit recovers the high-spee d receive clock from the incoming scrambled nrz dat a stream. the recovered serial data is converted into 4-bit-wide 622.08/666.51 mbps parallel data and pr esented to the rxd[3:0]p/n lvds parallel interface. a divid e-by-4 version of the high-speed recovered clock, rxpclkop/n, is used to synchronize the transfer of the 4-bit rxdo[3:0]p/n data with the receive portio n of the upstream device. upon initialization or loss of signal or loss of lock the 77.76/155.52 mhz (83.31 /166.63 mhz) external local reference clock is used to star t-up the clock recovery phase-locked loop for prope r operation. a special loop-back feature can be confi gured when parallel remote loopback (rloopp) is use d in conjunction with de-jittered loop-time mode that al lows the re-transmitted data to comply with itu and bellcore jitter generation specifications. 2.1 receive serial input the receive serial cml inputs are applied to rxip/n . the receive serial inputs can be ac or dc coupled to an optical module or an electrical interface. a simpl ified ac coupled block diagram is shown in figure 4. n ote : some optical modules integrate ac coupled capacitor s within the module. if so, the external ac couple d capacitors are not necessary and can be excluded. the 2.488/2.666 gbps high-speed differential cml rx ip/n input swing characteristics is shown in table 2 . f igure 4. r eceive s erial i nput i nterface b lock t able 2: d ifferential cml i nput s wing p arameters p arameter d escription m in t yp m ax u nits d v indiff differential input voltage swing 200 1000 mv d v inse single-ended input voltage swing 100 600 mv d v inbias input bias range (ac coupled) 1.0 1.4 v r diff differential input resistance 75 125 w xrt91l80 sts-48/ stm-16 transceiver optical module 0.1 m f 0.1 m f rxip rxin optical fiber
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 15 2.2 receive clock and data recovery the clock and data recovery unit accepts the high s peed nrz serial data from the differential cml rece iver and generates a clock that is the same frequency as the incoming data. the clock recovery utilizes the refclkp/n to train and monitor its clock recovery p ll. initially upon startup, the pll locks to the lo cal reference clock within 500 ppm. once this is achie ved, the pll then attempts to lock onto the incomin g receive data stream. whenever the recovered clock f requency deviates from the local reference clock frequency by more than approximately 500 ppm, the clock recovery pll will switch and lock back onto t he local reference clock. when this condition occurs t he pll will declare loss of lock and the lockdet_cd r signal will be pulled "low." whenever a loss of loc k/loss of signal detection (losd) event occurs, the cdr will continue to supply a receive clock (based on t he local reference clock) to the upstream framer de vice. a loss of lock condition will also be declared when the external sdext becomes inactive. when the sdext is de-asserted by the optical module and losdmute is e nabled, receive parallel data output will be forced to a logic zero state for the entire duration that a los d condition is detected. this acts as a receive dat a mute upon losd function to prevent random noise from being mi sinterpreted as valid incoming data. when sdext becomes active and the recovered clock is determine d to be within 500 ppm accuracy with respect to th e local reference source, the clock recovery pll will switch and lock back onto the incoming receive dat a stream and the lock detect output (lockdet_cdr) will go ac tive. table 3 specifies the clock and data recovery unit performance characteristics. t able 3: c lock and d ata r ecovery u nit p erformance jitter specification is defined using a 12khz to 20 mhz appropriate sonet/sdh filter. 1 required to meet sonet output frequency stability r equirements. 2.3 external signal detection xrt91l80 supports external signal detection (sdext) . the external signal detect function is supported by the sdext input. this input is coming from the opti cal module through an output usually called sd or flag which indicates the lack or presence of optical pow er. depending on the manufacturer of these devices, the polarity of this signal can be either active "low" or active "high." the sdext and polarity inputs are exclusive ored to generate the external losdet sig nal, internal loss of signal detect (losd) declarat ion and mute upon losd control signal. whenever an exte rnal sd is absent, the xrt91l80 will automatically output a high level signal on the losdet output pin as well as update the control registers whenever t he host mode serial microprocessor interface feature is act ive. if losdmute is enabled, it will force the rece ive parallel data output to a logic state "0" for the e ntire duration that a losd condition is declared. t his acts as a receive data mute upon losd function to prevent ran dom noise from being misinterpreted as valid incomi ng data. table 4 specifies sdext declaration polarity s ettings. n ame p arameter m in t yp m ax u nits ref duty reference clock duty cycle 45 55 % ref tol reference clock frequency tolerance 1 -20 +20 ppm oclk jit clock output jitter generation with 77.76 mhz refer ence clock 3.5 5.0 mui rms oclk jit clock output jitter generation with 155.52 mhz refe rence clock 3.7 5.0 mui rms tol jit input jitter tolerance with 1 mhz < f < 20 mhz prbs pattern 0.4 0.7 ui oclk freq frequency output 2.488 2.667 ghz oclk duty clock output duty cycle 45 55 %
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 16 2.4 receive serial input to parallel output (sipo) the sipo is used to convert the 2.488/2.666 gbps se rial data input to 622.08/666.51 mbps parallel data output which can interface to a sonet framer/asic. the sip o bit de-interleaves the serial data input into a 4 -bit parallel output to rxdo[3:0]p/n. a simplified bloc k diagram is shown in figure 5. 2.5 receive parallel output interface the 4-bit lvds 622.08/666.51 mbps parallel data out put of the receive path is used to interface to a s onet framer/asic synchronized to the recovered clock. a simplified block diagram is shown in figure 6. t able 4: losd d eclaration p olarity s etting sdext polarity losdmute i nternal s ignal d etect losdet o utput rxdo[3:0]p/n cdr pll r eference l ock 0 0 1 active low. optical signal presence indicated by sdext logic 0 input from optical module. low normal operation hi-spd received data 0 1 1 active high. optical signal presence indicated by sdext logic 1 input from optical module. high losd declared muted local reference clock 1 0 1 active low. optical signal presence indicated by sdext logic 0 input from optical module. high losd declared muted local reference clock 1 1 1 active high. optical signal presence indicated by sdext logic 1 input from optical module. low normal operation hi-spd received data f igure 5. s implified b lock d iagram of sipo f igure 6. r eceive p arallel o utput i nterface b lock b 0 0 b 0 1 b 0 2 b 0 3 b 1 0 b 1 1 b 1 2 b 1 3 b 2 0 b 2 1 b 2 2 b 2 3 b 3 0 b 3 1 b 3 2 b 3 3 4-bit parallel lvds data output rxdo0p/n rxdo3p/n rxdo2p/n rxdo1p/n rxip/n rxpclkop/n 622.08/666.51 mhz b 3 0 b 2 0 b 1 0 b 0 0 b 3 1 b 2 1 b 1 1 b 0 1 b 3 2 b 2 2 b 1 2 b 0 2 b 0 3 b 1 3 b 2 3 b 3 3 2.488/2.666 gbps sipo time (0) sonet framer/asic xrt91l80 sts-48/stm-16 transceiver rxdo0p/n rxdo1p/n rxdo3p/n rxdo2p/n rxpclkop/n losdmute disrd polarity sdext rxclko16p/n
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 17 2.6 receive parallel interface lvds operation when operating the 4-bit differential bus in lvds m ode, a 402 w external resistor is needed across xres1p and xres1n to properly bias the rxdo[3:0]p/n and rx pclkop/n pins. figure 7 shows the proper biasing resistor installed. 2.7 parallel receive data output mute upon losd the parallel receiver data outputs can be automatic ally forced "low" during an losd condition to preve nt data chattering. however, the user must select the prope r sdext polarity for the optical module used. by as serting losdmute "high", the parallel receiver data outputs will be forced "low" any time an losd condition oc curs. 2.8 parallel receive data output disable unlike losdmute, disrd is used to asynchronously fo rce the parallel receiver data outputs to zero, regardless of the data input stream. by asserting disrd "high", the parallel receiver data outputs wi ll immediately mute. 2.9 receive parallel data output timing the receive parallel data output from the sts-48/st m-16 receiver will adhere to the setup and hold tim es shown in figure 8 and table 5. f igure 8. r eceive p arallel o utput t iming t able 5: r eceive p arallel d ata and c lock o utput t iming s pecifications f igure 7. lvds external biasing resistors s ymbol p arameter m in t yp m ax u nits t rxpclko receive parallel clock output period (622.08 mhz no n-fec rate) 1608 ps t rxpclko receive parallel clock output period (666.51 mhz fe c rate) 1500 ps t rx_inv rxpclkop/n "high" to data invalid window 200 ps t rx_del rxpclkop/n "high" to data delay 200 ps rx duty rxpclkop/n duty cycle 45 55 % xres1n xres1p 402 w +/- 1 % tolerance pin g1 pin f1 rxpclkop/n rxdo[3:0]p/n t rx_inv t rxpclko t rx_inv t rx_del sample window t rx_del
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 18 3.0 transmit section the transmit section of the xrt91l80 accepts 4-bit parallel lvds data and converts it to serial cml da ta output intented to interface to an optical module. it consists of a 4-bit parallel lvds interface, a 4 x9 fifo, parallel-to-serial converter, a clock multiplier un it (cmu), a current mode logic (cml) differential l ine driver, and loop timing modes. the cml serial data output r ate is 2.488/2.666 gbps for sts-48/stm-16 applications. the high frequency serial clock is sy nthesized by a pll, which uses a low frequency cloc k as its input reference. in order to synchronize the data transfer process, the synthesized 2.488/2.666 ghz s erial clock output is divided by four and the 622.08/666. 51 mhz clock is presented to the upstream device to be used as its timing source. 3.1 transmit parallel input interface the parallel data from an upstream device is presen ted to the xrt91l80 through a 4-bit lvds parallel b us interface txdi[3:0]p/n. the data is latched into a parallel input register on the rising edge of txpcl kip/n. if the sonet framer/asic is synchronized to the same t iming source as the xrt91l80, the transmit data and clock input can directly interface to the sts-48/st m-16 transceiver. however, if the sonet framer/asic is synchronized to a separate crystal, the xrt91l80 ha s two clock output references that can be used to synchronize the sonet framer/asic. txpclkop/n is a 622.08/666.51 mhz lvds clock output source that is derived from the cmu synthesized high-speed cloc k. txclko16p/n is a 155.52/166.63 mhz lvds auxiliary clock output source that is also derived from the cmu synthesized high-speed clock. either o f these two clock output sources can be used to synchronize the sonet framer/asic to the xrt91l80. if the auxiliary clock source is not used, it can be disab led by pulling txclko16dis "high". a simplified blo ck diagram of the parallel interface is shown in figur e 9. f igure 9. t ransmit p arallel i nput i nterface b lock sonet framer/asic txdi0p/n txdi1p/n txdi3p/n txdi2p/n txpclkip/n txpclkop/n txclko16p/n txclko16disp/n xrt91l80 sts-48/stm-16 transceiver
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 19 3.2 transmit parallel data input timing when applying parallel data input to the transmitte r, the setup and hold times should be followed as s hown in figure 10 and table 6. f igure 10. t ransmit p arallel i nput t iming t able 6: t ransmit p arallel d ata and c lock i nput t iming s pecification t able 7: t ransmit p arallel c lock o utput t iming s pecification 3.3 transmit fifo the parallel interface also includes a 4x9 fifo tha t can be used to eliminate difficult timing issues between the input transmit clock and the clock derived from the cmu. the use of the fifo permits the system to tol erate an arbitrary amount of delay and jitter between txpclk op/n and txpclkip/n. the fifo can be initialized when fifo_rst is asserted and held "high" for 2 cyc les of the txpclkop/n clock. when the fifo_rst is de-asserted, it will take 8 to 10 txpclkop/n cycles for the fifo to flush out. once the fifo is center ed, the delay between txpclkop/n and txpclkip/n can decreas e or increase up to two periods of the low-speed clock. should the delay exceed this amount, the rea d and write pointers will point to the same nibble in the fifo resulting in a loss of transmitted data (fifo overflow). in the event of a fifo overflow, the fif o control logic will initiate an overflow signal that can be used by an external controller to issue a fifo rese t signal. the device under the control of the fifo_au torst pin can automatically recover from an overflo w condition. when the fifo_autorst input is set to a "high" level, once an overflow condition is detecte d, the s ymbol p arameter m in t yp m ax u nits t txpclki transmit parallel clock input period (622.08 mhz n on-fec rate) 1608 ps t txpclki transmit parallel clock input period (666.51 mhz f ec rate) 1500 ps t txdi_su txpclkip/n "high" to data setup time 300 ps t txdi_hd txpclkip/n "high" to data hold time 300 ps tx duty txpclkip/n duty cycle 40 60 % s ymbol p arameter m in t yp m ax u nits t txpclko transmit parallel clock output period (622.08 mhz non-fec rate) 1608 ps t txpclko transmit parallel clock output period (666.51 mhz fec rate) 1500 ps tx duty txpclkop/n duty cycle 45 55 % txpclkip/n txdi[15:0]p/n t txdi_su t txdi_hd t txpclki t txpclko txpclkop/n
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 20 device will set the overflow pin to a "high" level and will automatically reset and center the fifo. f igure 11 provides a detailed overview of the transmit fifo i n a system interface. f igure 11. t ransmit fifo and s ystem i nterface 3.4 fifo calibration upon power up it is required that the fifo_rst pin be pulled "hig h" for 2 txpclkop/n cycles to flush out the fifo af ter the device is powered on. if the fifo experiences an ov erflow condition, fifo_rst can be used to manually reset the fifo. however, the sts-48/stm-16 transcei ver has an automatic reset pin that will allow the fifo to automatically reset upon an overflow condition. fif o_autorst should be pulled "high" to enable the automatic fifo reset function. 3.5 transmit parallel input to serial output (piso) the piso is used to convert 622.08/666.51 mhz paral lel data input to 2.488/2.666 gbps serial data outp ut which can interface to an optical module. the piso bit interleaves parallel data input into a serial bit stream taking the first bit from txdi3p/n, then the first bit from txdi2p/n, and so on as shown in figure 12. f igure 12. s implified b lock d iagram of piso write pointer read pointer autorst overflow reset txpclkip/n refclkp/n fifo control div by 4 2.488/2.666 ghz pll cmu delay upstream device 4 x 9 fifo xrt91l80 txpclkop/n 4 txdi[3:0]p/n 4 b 0 0 b 0 1 b 0 2 b 0 3 b 0 4 b 0 5 b 0 6 b 0 7 b 1 0 b 1 1 b 1 2 b 1 3 b 1 4 b 1 5 b 1 6 b 1 7 b 2 0 b 2 1 b 2 2 b 2 3 b 2 4 b 2 5 b 2 6 b 2 7 b 3 0 b 3 1 b 3 2 b 3 3 b 3 4 b 3 5 b 3 6 b 3 7 4-bit parallel lvds data input txdi0p/n txdi3p/n txdi2p/n txdi1p/n txop/n txpclkip/n 622.08/666.51 mhz 2.488/2.666 gbps b 0 0 b 1 0 b 2 0 b 3 0 b 0 1 b 1 1 b 2 1 b 3 1 b 0 2 b 1 2 b 2 2 b 3 2 b 0 3 b 1 3 b 2 3 b 3 3 piso time (0)
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 21 3.6 clock multiplier unit (cmu) and re-timer the high-speed serial clock synthesized by the cmu is divided by 4, and is presented to the upstream d evice as txpclkop/n clock . the upstream device should us e txpclkop/n as its timing source. the upstream device then generates the txpclkip/n clock that is phase aligned with the transmit data and provides i t to the parallel interface of the transmitter. the data mus t meet setup and hold times with respect to txpclki p/n. the xrt91l80 will latch txdi[3:0]p/n on the rising edge of txpclkip/n. the clock synthesizer uses a p ll to lock to the differential input reference clock r efclkp/n. it will then use this reference clock to generate the 2.488/2.666 ghz sts-48/stm-16 serial clock and in a ddition feed this high-speed synthesized clock to t he piso. the retimer will then align the transmit seri al data from the piso with this 2.488/2.666 ghz syn thesized clock to generate the output txop/n. refclkp/n inp ut can accept a clock from a differential lvpecl cr ystal oscillator that has a frequency accuracy better tha n 20ppm in order for the high-speed transmit serial clock frequency to have the accuracy required for sonet s ystems. table 8 specifies the clock multiplier unit performance characteristics. the cmu can also be driven by an optional external vcxo for loop timed or local reference de-jitter applications. vcxo_inp/n can be connected to the ou tput of a vcxo that can be configured to clean up t he recovered received clock coming from cp_out in loop timing mode before being applied to the input of t he transmit cmu as a reference clock. in addition, the internal phase/frequency detector and charge pump, combined with an external vcxo can alternately be u sed as a jitter attenuator to de-jitter a noisy sys tem reference clock such as refclkp/n prior to it being used to time the cmu. the following section 3.7, l oop timing and clock control, on page 21 illustrate the use of this method. t able 8: c lock m ultiplier u nit p erformance jitter specification is defined using a 12khz to 20 mhz appropriate sonet/sdh filter. 1 required to meet sonet output frequency stability r equirements. 3.7 loop timing and clock control two types of loop timing are possible in the xrt91l 80. in the regular loop timing mode (without an externa l vcxo), loop timing is controlled by the looptm_no ja pin. this mode is selected by asserting the looptm_ noja signal to a "high" level. when the loop timing mode is activated, the external local reference clo ck to the input of the cmu is replaced with the 1/1 6th or the 1/32nd of the high-speed recovered receive clock co ming from the cdr. under this condition both the tr ansmit and receive sections are synchronized to the recove red receive clock. the normal looptime mode directl y locks the cmu to the recovered receive clock with no exte rnal de-jittering. loop timing performance can be further improved usi ng an external vcxo-based pll to clean up the jitte r of the recovered receive clock. in this case the vcxo_ sel pin should be set "high." by doing so, the cmu receives its reference clock signal from an externa l vcxo connected to the vcxo_inp/n inputs. the looptm_ja pin must also be set "high" in order to s elect the recovered receive clock as the reference source for the de-jitter pll. in this state, the vcxo will be phase locked to the recovered receive clock thr ough a narrowband loop filter. the use of the on-chip phas e/frequency detector with charge pump and an extern al vcxo to remove the transmit jitter due to jitter in the recovered clock is shown in figure 13. n ame p arameter m in t yp m ax u nits ref duty reference clock duty cycle 45 55 % ref tol reference clock frequency tolerance 1 -20 +20 ppm ref sts48 reference clock jitter limits from 12 khz to 20 mhz -61 db c oclk jit clock output jitter generation with 77.76 mhz refer ence clock 3.1 4.0 mui rms oclk jit clock output jitter generation with 155.52 mhz refe rence clock 2.5 3.0 mui rms oclk freq frequency output 2.488 2.667 ghz oclk duty clock output duty cycle 45 55 %
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 22 the on-chip phase/frequency detector can also be us ed to remove the jitter from a noisy reference sign al that is applied to the refclkp/n inputs. in this case, t he looptm_noja pin should be set "low", the vcxo_sel set "high", and the looptm_ja pin set "low ". in this configuration, the refclkp/n signal is used as the reference to the de-jitter pll and the de-jittered output of the phase locked vcxo is used as the timing reference to the cmu. table 9 provides config uration for selecting the loop timing and reference de-jitter modes. t able 9: l oop timing and reference de - jitter configurations vcxo_sel looptm_ja looptm_noja a ction 0 0 0 normal mode 0 0 1 loop timing without de-jitter vcxo 1 0 0 refclkp/n reference de-jitter vcxo 1 1 0 loop timing with de-jitter vcxo f igure 13. l oop t iming m ode u sing an e xternal c leanup vcxo vcxo_lock looptm_ja rxip rxin phase detect cdr mux loop filter div by 16 or 32 clk data ~~ ~~ vcxo xrt91l80 cpout 2.488/2.666ghz retimer looptm_noja lockdet_cmu vcxo_sel charge pump mux 1 0 1 0 piso mux 0 1 2.488/2.666ghz cmu txop txon vcxo_inp vcxo_inn refclkp refclkn altfreqsel
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 23 3.8 external loop filter as shown in figure 13, there is an internal charge p ump used to drive an external loop filter and exter nal vcxo. the charge pump current is fixed at 250ua. f igure 14 is a simplified block diagram of the extern al loop filter and recommended values. f igure 14. s implified d iagram of the e xternal l oop f ilter 3.9 transmit serial output control the 2.488/2.666 gbps transmit serial output is aval iable on txop/n pins. the transmit serial output ca n be ac or dc coupled to an optical module or electrical in terface. a simplified ac coupling block diagram is shown in figure 15. n ote : some optical modules integrate ac coupled capacitor s within the module. if so, the external ac couple d capacitors are not necessary and can be excluded. f igure 15. t ransmit s erial o utput i nterface block 300pf 1uf cp out vcxo 4.02k w xrt91l80 sts-48/ stm-16 transceiver optical module 0.1 m f 0.1 m f txop txon optical fiber
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 24 4.0 diagnostic features 4.1 serial remote loopback the serial remote loopback function is activated by setting rloops "high". when serial remote loopback is activated, the high-speed serial receive data from rxip/n is presented at the high-speed transmit outp ut txop/n, and the high-speed recovered clock is selec ted and presented to the high-speed transmit clock input of the retimer. during serial remote loopback, the high-speed receive data (rxip/n) is also converted to parallel data and presented at the low-speed receiv e parallel interface rxdo[3:0]p/n. the recovered re ceive clock is also divided by 4 and presented at the low -speed clock output rxpclkop/n to synchronize the transfer of the 4-bit received parallel data. a si mplified block diagram of serial remote loopback is shown in figure 16. 4.2 parallel remote loopback rloopp controls a more comprehensive version of rem ote loop-back that can also be used in conjunction with the de-jitter pll that is phase locked to the recovered receive clock. in this mode, the receive d signal is processed by the cdr, and is sent through the seria l to parallel converter. at this point, the 4-bit p arallel data and clock are looped back to the transmit fifo. con currently, if receive clock jitter attenuation is a lso employed, the received clock is divided down in fre quency and presented to the input of the integrated phase/ frequency detector and is compared to the frequency of a vcxo that is connected to the vcxo_inp/n inpu ts. with the looptm_ja configured to use the recovered receive clock as the reference and vcxo_sel asserted, the vcxo is phase locked to the recovered receive clock. the de-jittered clock is then used to retime the transmitter, resulting in the re-transmission o f the de-jittered received data out of txop/n. a f ifo reset using fifo_rst should follow immediately after enab ling/disabling parallel remote loopback. a simplifi ed block diagram of parallel remote loopback is shown in figure 17. f igure 16. s erial r emote l oopback f igure 17. p arallel r emote l oopback piso re-timer cml output drivers fifo sipo cdr cml input drivers serial remote loopback rx parallel output tx serial output rx serial input piso re-timer cml output drivers fifo sipo cdr cml input drivers parallel remote loopback rx parallel output tx serial output rx serial input
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 25 4.3 digital local loopback the digital local loopback is activated when the dl oop signal is set "high." when digital local loopba ck is activated, the high-speed data from the output of t he parallel to serial converter is looped back and presented to the high-speed input of the receiver serial to p arallel converter. the cmu output is also looped ba ck to the receive section and is used to synchronize the tran sfer of the data through the receiver. in digital l oopback mode, the transmit data from the transmit parallel interface txdi[3:0]p/n is serialized and presented to the high-speed transmit output txop/n using the high-sp eed 2.488/2.666 ghz transmit clock which is generat ed from the clock multiplier unit and presented to the input of the retimer and sipo. a simplified block diagram of digital loopback is shown in figure 18. f igure 18. d igital l oopback piso re-timer cml output drivers fifo sipo cdr cml input drivers digital loopback tx parallel input rx parallel output tx serial output
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 26 4.4 sonet jitter requirements sonet equipment jitter requirements are specified f or the following three types of jitter. the definit ions of each of these types of jitter are given below. sonet equ ipment jitter requirements are specified for the fo llowing three types of jitter. 4.4.1 jitter tolerance: jitter tolerance is defined as the peak-to-peak amp litude of sinusoidal jitter applied on the input oc -n equipment interface that causes an equivalent 1db o ptical power penalty. oc-1/sts-1, oc-3/sts-3, oc-12 / sts-12 and oc-48/sts-48 category ii sonet interface s should tolerate, the input jitter applied accordi ng to the mask of figure 19, with the corresponding parame ters specified in the figure. f igure 19. j itter t olerance m ask oc-n/sts-n level 13 12 48 f0 (hz) 10 10 10 10 f1 (hz) 30 30 30 600 f2 (hz) 300 300 300 6000 f3 (hz) 2k 6.5k 25k 100k f4 (hz) 20k 65k 250k 1000k a1 (uipp) 0.15 0.15 0.15 0.15 a2 (uipp) 1.5 1.5 1.5 1.5 a3 (uipp) 15 15 15 15 input jitter amplitude (ui pp ) a 3 a 2 a 1 f 0 f 1 f 2 f 3 f 4 slope= -20db/decade slope= -20db/decade jitter frequency (hz) 48 10 600 15 6000 100k 1000k 0.15 1.5
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 27 f igure 20. 91l80 m easured jitter tolerance with external jitter attenuation enabled in looptiming at 2.488 g bps in sts-48. 4.4.2 jitter transfer jitter transfer is defined as the ratio of the jitt er on the output of sts-n to the jitter applied on the input of sts-n versus frequency. jitter transfer is importan t in applications where the system is utilized in t he loop- timed mode, where the recovered clock is used as th e source of the transmit clock. f igure 21. 91l80 m easured jitter transfer with external jitter attenuation enabled in looptiming at 2.488 g bps in sts-48.
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 28 4.4.3 jitter generation jitter generation is defined as the amount of jitte r at the sts-n output in the absence of applied inp ut jitter. the bellcore and itu requirement for this type jitter i s 0.01ui rms measured with a specific band-pass fil ter. for more information on these specifications refer to bellcore tr-nwt-000253 sections 5.6.2-5 and gr-2 53- core section 5.6. f igure 22. 91l80 m easured e lectrical p hase n oise t ransmit j itter g eneration at 2.488 g bps wide-band filter used in this test case. f igure 23. 91l80 m easured e lectrical p hase n oise r eceive j itter g eneration at 2.488 g bps wide-band filter used in this test case. p h a s e n o i s e t r a n s m i t j i t t e r g e n e r a t i o n ( w i d e b a n d ) u s i n g h p 8 5 6 0 e - 1 3 5 - 1 3 0 - 1 2 5 - 1 2 0 - 1 1 5 - 1 1 0 - 1 0 5 - 1 0 0 - 9 5 - 9 0 - 8 5 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 f r e q u e n c y ( k h z ) db c /hz r e f c l k = 1 5 5 . 5 2 m h z r e f c l k = 7 7 . 7 6 m h z p h a se n o i se r e c e i v e j i tte r g e n e r a ti o n (w i d e b a n d ) u si n g h p 8 5 6 0 e -1 3 5 -1 3 0 -1 2 5 -1 2 0 -1 1 5 -1 1 0 -1 0 5 -1 0 0 -9 5 -9 0 -8 5 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 f r e q u e n c y ( k h z ) db c /hz r e f c l k = 1 5 5 . 5 2 m h z r e f c l k = 7 7 . 7 6 m h z
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 29 5.0 serial microprocessor interface block the serial microprocessor uses a standard 3-pin ser ial port with cs , sclk, and sdi for programming the transceiver. optional pins such as sdo, int , and reset allow the ability to read back contents of the registers, monitor the transceiver via an interrupt pin, and reset the transceiver to its default conf iguration by pulling reset "low" for more than 10ms. a simplifi ed block diagram of the serial microprocessor is sh own in figure 24. f igure 24. s implified b lock d iagram of the s erial m icroprocessor i nterface 5.1 s erial t iming i nformation the serial port requires 16 bits of data applied to the sdi (serial data input) pin. the serial micro processor samples sdi on the rising edge of sclk (serial cloc k input). the data is not latched into the device until all 16 bits of serial data have been sampled. a timing di agram of the serial microprocessor is shown in figu re 25. f igure 25. t iming d iagram for the s erial m icroprocessor i nterface n ote : the serial microprocessor interface does not support "burst write" or "burst read" operations. chip select (active "low") must be de-asserted at the end of every single write or single read op eration. serial microprocessor interface cs sdi sclk sdo reset int hw/host cs sdi sclk sdo 1 2 10 9 8 7 6 5 4 3 11 16 15 13 14 12 r/w a0 a1 a2 a3 a4 a5 x d0 d1 d7 d6 d5 d4 d3 d2 d0 d1 d7 d6 d5 d4 d3 d2 high-z high-z 25ns 50ns
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 30 5.2 16-b it s erial d ata i nput d escritption the serial data input is sampled on the rising edge of sclk. in readback mode, the serial data output is updated on the falling edge of sclk. the serial da ta must be applied to the transceiver lsb first. t he 16 bits of serial data are described below. 5.2.1 r/w (sclk1) the first serial bit applied to the transceiver inf orms the microprocessor that a read or write operat ion is desired. if the r/w bit is set to 0, the micropr ocessor is configured for a write operation. if th e r/w bit is set to 1, the microprocessor is configured for a read operation. 5.2.2 a[5:0] (sclk2 - sclk7) the next 6 sclk cycles are used to provide the addr ess to which a read or write operation will occur. a0 (lsb) must be sent to the transceiver first followe d by a1 and so forth until all 6 address bits have been sampled by sclk. 5.2.3 x (dummy bit sclk8) the dummy bit sampled by sclk8 is used to allow suf ficient time for the serial data output pin to upda te data if the readback mode is selected by setting r/w = 1. therefore, the state of this bit is ignored an d can hold either 0 or 1 during both read and write operat ions. 5.2.4 d[7:0] (sclk9 - sclk16) the next 8 sclk cycles are used to provide the data to be written into the internal register chosen by the ad- dress bits. d0 (lsb) must be sent to the transceiv er first followed by d1 and so forth until all 8 da ta bits have been sampled by sclk. once 16 sclk cycles have bee n complete, the transceiver holds the data until cs is pulled high whereby, the serial microprocessor la tches the data into the selected internal register. 5.3 8-b it s erial d ata o utput d escription the serial data output is updated on the falling ed ge of sclk9 - sclk16 if r/w is set to 1. d0 (lsb ) is pro- vided on sclk9 to the sdo pin first followed by d1 and so forth until all 8 data bits have been update d. the sdo pin allows the user to read the contents stored in individual registers by providing the desired a ddress on the sdi pin during the read cycle.
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 31 6.0 register map and bit descriptions t able 11: m icroprocessor r egister 0 x 00 h b it d escription t able 10: m icroprocessor r egister m ap r eg addr t ype d7 d6 d5 d4 d3 d2 d1 d0 channel 0 control register (0x00h - 0x05h) 0 0x00 r/w reserved reserved reserved vcxoie losie cdrie cmuie fifoie 1 0x01 rur reserved reserved reserved vcxois losis cdris cmuis fifois 2 0x02 ro reserved reserved reserved vcxod losd cdrd cmud fifod 3 0x03 r/w reserved altfreqsel reserved loopbw vcxo_sel txclk016dis fifo_auto- rst fiforst 4 0x04 r/w reserved polarity looptm_ ja looptm_ noja losdmute disrd reserved vcxolken 5 0x05 r/w reserved reserved reserved reserved reserved dloop rloops rloopp 0x06 - 0x3d r/w reserved 62 0x3e ro device id (see bit description) 63 0x3f ro revision id (see bit description) i nterrupt e nable c ontrol r egister (0 x 00 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x x d6 reserved this register bit is not used x x d5 reserved this register bit is not used x x d4 vcxoie voltage controlled external oscillator lock interru pt enable "0" = masks the vcxo lock interrupt generation "1" = enables interrupt generation n ote : vcxolken must be enabled for this bit to have funct ional meaning. r/w 0 d3 losie loss of signal interrupt enable "0" = masks the los interrupt generation "1" = enables interrupt generation r/w 0 d2 cdrie clock and data recovery lock interrupt enable "0" = masks the cdr lock interrupt generation "1" = enables interrupt generation r/w 0 d1 cmuie clock multiplier unit lock interrupt enable "0" = masks the cmu lock interrupt generation "1" = enables interrupt generation r/w 0 d0 fifoie fifo overflow interrupt enable "0" = masks the fifo overflow interrupt generation "1" = enables interrupt generation r/w 0
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 32 t able 13: m icroprocessor r egister 0 x 02 h b it d escription t able 12: m icroprocessor r egister 0 x 01 h b it d escription i nterrupt s tatus c ontrol r egister (0 x 01 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x x d6 reserved this register bit is not used x x d5 reserved this register bit is not used x x d4 vcxois voltage controlled external oscillator lock interru pt status an external interrupt will not occur unless the vcx oie is set to "1" in the channel register 0x00h. "0" = no change "1" = change in vcxo lock status occurred n ote : vcxolken must be enabled for this bit to have funct ional meaning. rur 0 d3 losis loss of signal interrupt status an external interrupt will not occur unless the rlo sie is set to "1" in the channel register 0x00h. "0" = no change "1" = change in los status occurred rur 0 d2 cdris clock and data recovery lock interrupt status an external interrupt will not occur unless the cdr ie is set to "1" in the channel register 0x00h. "0" = no change "1" = change in cdr lock status occurred rur 0 d1 cmuis clock multiplier unit lock interrupt status an external interrupt will not occur unless the cmu ie is set to "1" in the channel register 0x00h. "0" = no change "1" = change in cmu lock status occurred rur 0 d0 fifois fifo overflow interrupt status an external interrupt will not occur unless the fif oie is set to "1" in the channel register 0x00h. "0" = no change "1" = change in fifo overflow status occurred rur 0 s tatus c ontrol r egister (0 x 02 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x x d6 reserved this register bit is not used x x
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 33 d5 reserved this register bit is not used x x d4 vcxod voltage controlled external oscillator lock detecti on the vcxod is used to indicate whether the internal clock refer- ence is locked to an external vco. "0" = vcxo currently not locked "1" = vcxo locked n ote : vcxolken must be enabled for this bit to have funct ional meaning. ro 0 d3 losd loss of signal detection the losd indicates the los activity. "0" = no alarm "1" = a los condition is present ro 0 d2 cdrd clock and data recovery lock detection the cdrd is used to indicate that the cdr is locked . "0" = cdr out of lock "1" = cdr locked ro 0 d1 cmud clock multiplier unit lock detection the cmud is used to indicate that the cmu is locked . "0" = cmu out of lock "1" = cmu locked ro 0 d0 fifod fifo overflow detection the fifod indicates that the fifo is experiencing a n overflow condition. "0" = no alarm "1" = a fifo overflow condition is present ro 0 t able 14: m icroprocessor r egister 0 x 03 h b it d escription c onfiguration 0 c ontrol r egister (0 x 03 h ) b it n ame f unction register type default value (hw reset) d7 reserved reserved - set to 0 r/w 0 d6 altfreqsel input reference frequency select this bit is used to select the clock input referenc e. "0" = 77.76/83.3 mhz "1"= 155.52/166 mhz r/w 1 d5 reserved reserved - set to 0 r/w 0 s tatus c ontrol r egister (0 x 02 h ) b it n ame f unction register type default value (hw reset)
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 34 d4 loopbw cmu loop band width select this bit is used to select the bandwidth of the clo ck multiplier unit of the transmit path to a narrow or wide band. use wide band for clean reference signals and narrow band for noisy r eferences. "0" = wide band (4x) "1" = narrow band (1x) r/w 0 d3 vcxo_sel vcxo de-jitter select this bit selects either the normal refclkp/n or the de-jitter vcxo_inp/n as a reference clock. "0" = normal refclkp/n mode "1" = de-jitter vcxo mode r/w 0 d2 txclko16dis auxiliary clock disable this bit is used to control the activity of the aux iliary clock. "0" = txclko16p/n enabled "1" = txclko16p/n disabled r/w 0 d1 fifo_ autorst automatic fifo overflow reset if this bit is set to "1", the sts-48/stm-16 transc eiver will automat- ically flush the fifo upon an overflow condition. upon power-up, the fifo should be manually reset by setting fifo_r st to "1" for a minimum of 2 txpclkop/n cycles. "0" = manual fifo reset required for overflow condi tions "1" = automatically resets fifo upon overflow detec tion r/w 0 d0 fifo_rst manual fifo reset fiforst should be set to "1" for a minimum of 2 txp clkop/n cycles after powering up and during manual fifo res et. after the fifo_rst bit is returned "low," it will take 8 to 1 0 txpclkop/n cycles for the fifo to flush out. upon an interrup t indication that the fifo has an overflow condition, this bit is use d to reset or flush out the fifo. "0" = normal operation "1" = manual fifo reset n ote : to automatically reset the fifo, see the fifo_autor st bit. r/w 0 t able 14: m icroprocessor r egister 0 x 03 h b it d escription c onfiguration 0 c ontrol r egister (0 x 03 h ) b it n ame f unction register type default value (hw reset)
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 35 t able 15: m icroprocessor r egister 0 x 04 h b it d escription t able 16: m icroprocessor r egister 0 x 05 h b it d escription c onfiguration 1 c ontrol r egister (0 x 04 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x x d6 polarity polarity for sdext input controls the signal detect polarity convention of s dext. "0" = sdext is active "low" "1" = sdext is active "high" r/w 0 d5 looptm_ja loop timing with jitter attenuation the looptm_ja bit must be set to "1" in order to se lect the recov- ered receive clock as the reference source for the de-jitter pll. "0" = disabled "1" = loop timing with de-jitter pll activated r/w 0 d4 looptm_ noja loop timing with no jitter attenuation when the loop timing mode is activated, the externa l local refer- ence clock input to the cmu is replaced with the 1/ 16th or 1/32nd of the high-speed recovered receive clock coming fr om the cdr. "0" = disabled "1" = loop timing activated r/w 0 d3 losdmute parallel receive data output mute upon losd if this bit is set to "1", the receive data output will automatically be forced to a logic state of "0" when an losd conditi on occurs. "0" = disabled "1" = mute rxdo[3:0]p/n data upon losd condition r/w 0 d2 disrd parallel receive data output disable this bit is used to disable the rxdo[3:0]p/n parall el receive data output bus asynchronously. "0" = normal mode "1" = forces rxdo[3:0]p/n to a logic state "0" r/w 0 d1 reserved reserved - set to 0 r/w 0 d0 vcxolken de-jitter pll lock detect enable this bit enables the vcxo_inp/n lock detect circuit to be active. "0" = vcxo lock detect disabled "1" = vcxo lock detect enabled r/w 0 d iagnostic c ontrol r egister (0 x 05 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x x d6 reserved this register bit is not used x x
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 36 d5 reserved this register bit is not used x x d4 reserved this register bit is not used x x d3 reserved this register bit is not used x x d2 dloop digital local loopback digital local loopback allows the transmit input pi ns to be looped back to the receive output pins for local diagnosti cs. the transmit serial data output is valid during the digital loop back. "0" = disabled "1" = enable digital local loopback n ote : dloop and rloops can be enabled simultaneously to achieve a dual loopback diagnostic feature. r/w 0 d1 rloops serial remote loopback serial remote loopback allows the receive serial in put pins to be looped back to the transmit serial output pins for remote diagnos- tics. the receive data output is valid during a se rial remote loop- back. "0" = disabled "1" = enable remote serial loopback n ote : dloop and rloops can be enabled simultaneously to achieve a dual loopback diagnostic feature. r/w 0 d0 rloopp parallel remote loopback parallel remote loopback has the same affect as the serial remote loopback, except that the data input is allowed to pass through the sipo before its looped back to the transmit path, wherein it passes through the transmit fifo, through the piso, and back out the transmit serial output. the receive data outpu t is valid during a parallel remote loopback. "0" = disabled "1" = enable remote parallel loopback n ote : dloop and rloops should be disabled when rloopp is enabled. the internal fifo should also be flushe d using fifo_rst when parallel remote loopback is enabled/ disabled. r/w 0 d iagnostic c ontrol r egister (0 x 05 h ) b it n ame f unction register type default value (hw reset)
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 37 t able 17: m icroprocessor r egister 0 x 3e h b it d escription t able 18: m icroprocessor r egister 0 x 3f h b it d escription d evice "id" r egister (0 x 3e h ) b it n ame f unction register type default value (hw reset) d7 d6 d5 d4 d3 d2 d1 d0 device "id" the device "id" of the xrt91l80 liu is 0 xc0h. along with the revision "id", the device "id" is used to enable so ftware to identify the silicon adding flexibility for system control a nd debug. ro 1 10 0 0 0 0 0 r evision "id" r egister (0 x 3f h ) b it n ame f unction register type default value (hw reset) d7 d6 d5 d4 d3 d2 d1 d0 revision "id" the revision "id" of the xrt91l80 liu is used to en able software to identify which revision of silicon is currently being tested. the revision "id" for the first revision of silicon (re vision a) will be 0x01h. ro this byte shows the revision of the device.
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 38 7.0 electrical characteristics absolute maximum ratings n ote : stresses listed under absolute maximum power and i/ o ratings may be applied to devices one at a time w ithout causing permanent damage. functionality at or above the values listed is not implied. exposure to thes e values for extended periods will severely affect device reliab ility. thermal resistance of stbga package.... q ja = 44 c/w operating temperature range.................-40c t o 85c thermal resistance of stbga package.... q jc = 12 c/w case temperature under bias..................-55c to 125c esd protection (hbm)............................... ...........>2000v storage temperature .............. .................-65c to 150c absolute maximum power and input/output ratings s ymbol t ype p arameter m in t yp m ax u nits vdd 1.8 1.8v digital core power supplies -0.5 3.6 v avdd 1.8 1.8v analog core power supplies -0.5 3.6 v vdd _io 3.3v digital i/o and power supply -0.5 6.0 v avdd _io 3.3v analog i/o and power supply -0.5 6.0 v lvpecl dc logic signal input voltage -0.5 vdd _io +0.5 v lvds dc logic signal input voltage -0.5 vdd _io +0.5 v lvttl/ lvcmos dc logic signal input voltage -0.5 5.5 v lvds dc logic signal output voltage -0.5 vdd _o +0.5 v lvcmos dc logic signal output voltage -0.5 vdd _o +0.5 v lvpecl input current -100 100 ma lvds input current -100 100 ma lvttl/ lvcmos input current -100 100 ma power and current dc electrical characteristics s ymbol t ype p arameter m in t yp m ax u nits c onditions vdd 1.8 cml and cmos core power supply voltage 1.710 1.8 1.890 v avdd 1.8_tx analog transmit cml and lvds power supply voltage (avdd1.8_tx) 1.710 1.8 1.890 v avdd 1.8_rx analog receive cml and lvds power supply voltage (avdd1.8_rx) 1.710 1.8 1.890 v vdd 3.3 lvpecl and digital i/o power supply voltage 3.135 3.3 3.465 v
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 39 common mode logic signal dc electrical characterist ics lvpecl logic signal dc electrical characteristics avdd 3.3_tx analog transmit i/o power supply voltage (avdd3.3_tx) 3.135 3.3 3.465 v avdd 3.3_rx analog receive i/o power supply voltage (avdd3.3_rx) 3.135 3.3 3.465 v i dd_1.8 1.8v total power supply current 262 ma i dd_io 3.3v total power supply current 5 ma p lvds total power dissipation 490 650 mw lvds mode test condition: vdd 1.8 = 1.8v + 5%, vdd _io = 3.3v + 5% unless otherwise specified s ymbol t ype p arameter m in t yp m ax u nits c onditions v odiff cml output differential voltage 800 1200 mv differential mode. v idiff cml input differential voltage 200 1000 mv differential mode. v isingle cml input single-ended voltage swing 100 600 mv differential mode. v ibias cml input bias range (ac coupled) 1.0 1.4 v differential mode. r diff cml input differential resistance 75 125 w test condition: vdd 1.8 = 1.8v + 5%, vdd _io = 3.3v + 5% unless otherwise specified s ymbol t ype p arameter m in t yp m ax u nits c onditions v ih lvpecl input high voltage vdd _io - 1.2 vdd _io - 0.7 v differential v il lvpecl input low voltage vdd _io - 2.0 vdd _io - 1.4 v differential v idiff lvpecl input differential voltage 0.4 2.4 v differential mode. v isingle lvpecl input single-ended voltage swing 0.2 1.2 v differential mode. power and current dc electrical characteristics s ymbol t ype p arameter m in t yp m ax u nits c onditions
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 40 lvds logic signal dc electrical characteristics lvttl/lvcmos signal dc electrical characteristics n ote : all input control pins are lvcmos and lvttl compati ble. all output control pins are lvcmos compatible only. test condition: vdd 1.8 = 1.8v + 5%, vdd _io = 3.3v + 5% unless otherwise specified s ymbol t ype p arameter m in t yp m ax u nits c onditions v oh lvds output high voltage 1480 mv 100 w line - line v ol lvds output low voltage 1020 mv 100 w line - line v odiff lvds output differential voltage swing 250 400 mv 100 w line - line v osingle lvds output single-ended voltage swing 125 200 mv 100 w line - line v ih lvds input high voltage 1400 mv v il lvds input low voltage 800 mv v idiff lvds input differential voltage swing 200 mv v isingle lvds input single-ended voltage swing 100 mv test condition: vdd 1.8 = 1.8v + 5%, vdd _io = 3.3v + 5% unless otherwise specified s ymbol t ype p arameter m in t yp m ax u nits c onditions v oh lvcmos output high voltage 2.4 v i oh = -1.0ma v ol lvcmos output low voltage 0.4 v i oh = 1.0ma v ih lvttl/ lvcmos input high voltage 2.0 v v il lvttl/ lvcmos input low voltage 0.8 v i leak lvttl/ lvcmos input leakage current -10 10 m a v in = vdd _io or v in = 0 i leak_pu lvttl/ lvcmos input leakage current with pull-up resistor 38 52 65 m a v in = 0 i leak_pd lvttl/ lvcmos input leakage current with pull-down resistor 32 43 55 m a v in = vdd _io
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 41 196 shrink thin ball grid array (12.0 mm x 12.0 mm, stbga) rev. 1.00 ordering information p art n umber p ackage o perating t emperature r ange xrt91l80ib 196 shrink thin ball grid array (12.0 mm x 12.0 mm, stbga) -40 c to +85 c (a1 corner feature is m fger option) a b e a1 a2 seating plane a 11 10 9 8 7 6 5 4 3 1 2 bc d e f g h j k l d d1 a1 feature/mark 13 14 12 p n m d1 d sym bol min max min max a 0.053 0.067 1.35 1.70 a1 0.010 0.022 0.25 0.55 a2 0.033 0.052 0.85 1.31 d 0.465 0.480 11.80 12.20 d1 0.409 bsc 10.40 bsc b 0.018 0.022 0.45 0.55 e 0.031 bsc 0.80 bsc inches millimeters note: the control dimension is in millimeter.
xrt91l80 preliminary xr xr xr xr 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r rev. p1.1.0 42 revision history r evision # d ate d escription p1.0.0 october 2004 1st release of the xrt91l80 produ ct brief p1.0.1 october 2004 fixed typos throughout document p1.0.2 october 2004 fixed typos throughout document p1.0.3 january 2005 added jitter transfer and toleran ce mask test results and phase noise transmit jitte r generation results, added cs de-assertion note on section 5.1, fixed register 0 x02, 0x04, 0x05 microprocessor bit descriptions, updated pin descriptions, corrected fall- ing edge typo in section 3.6 to rising edge, and enhanced receive and transmit interface block diagrams. p1.0.4 march 2005 remove rxsel reference on the rxi p/n pin description. minor edit in receive sec- tion 2.0. fifo_rst corrected for active high in sec tion 3.4. removed unsupported note for transparent mode fifo operation in section 3.3. p1.0.5 april 2005 1.design change: renamed disrd, tri rxd, and tritxclko16p/n to losd- mute, disrd, and txclko16dis respectively. correcte d and redefined pin defini- tions for losdmute, disrd, and txclko16dis. 2.renamed losext, reffreqsel, txclkip/n, rxclkp/n, rxd[3:0]p/n, rxclk16p/n, lptime_ja, lptime_no_ja, rxp/n to sdext , altfreqsel, txpclkip/n, rxpclkop/n, rxdo[3:0]p/n, rxclko16p/n, looptm_ja, looptm_noja, xres1p/n respectively. 3.updated stbga pinout names to include above menti oned changes. 4.corrected loopbw and rloopp pin descriptions. 5.corrected rxdo[3:0]p/n description error from up dated on rising edge to updated on falling edge of rxpclkop/n. 5.updated and improved all pin list decriptions and formatted table headers. 6.added jtag input pin pull-up and pull-down descri ptions. 7.removed unsupported note for transparent mode fif o operation in section 3.3 and enhanced and corrected fifo reset operation des cription. 8.moved fifo figure 11 from sect 3.6 to section 3.3. 9.corrected figure 13, loop timing mode using an ex ternal cleanup vcxo. 10.corrected loopback definition errors in section 4.0. 11.significantly enhanced sec. 2.3 "los" to "extern al signal detection, sec. 3.3 transmit fifo, and sec. 3.6 cmu and retimer, and se c. 3.7 loop timing and clock control. 12.enhanced transmit/receive parallel data and cloc k input/output timing diagram and tables. 13.added cmu and cdr performace tables. 14.added cml input swing characteristics table. 15.added losd declaration polarity setting tables. 16.added lvds biasing resistor diagram. 17.reformatted and enhanced ac/dc electrical charac teristics tables. 18.change mhz to mbps to reflect parallel data i/o and serial i/o more accurately. corrected and enhanced piso and sipo diagrams. 19.removed all reference to "differential limiting amplifier" and txo2p/n pins. 20.updated microprocessor register bits and descrip tions to reflect changes. 21.added microprocessor register names. 22.retouched 91l80 block diagram. 23.changed oc-48 name to sts-48. 24.minor edits and spelling and grammatical correct ions.
xr xr xr xr preliminary xrt91l80 rev. p1.1.0 2.488/2.666 gbps sts-48/stm-16 sonet/sdh transceive r 43 notice exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve design, performance or reliability. exar co rporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representa tion that the circuits are free of patent infringement. chart s and schedules contained here in are only for illu stration purposes and may vary depending upon a users speci fic application. while the information in this publ ication has been carefully checked; no responsibility, howe ver, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonabl y be expected to cause failure of the life support system or to significantly affect its safety or effectiveness . products are not authorized for use in such appli cations unless exar corporation receives, in writing, assurances t o its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; (c) potential liability of exar corporation is ad equately protected under the circumstances. copyright 2005 exar corporation datasheet july 2005. reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited. p1.0.6 july 2005 1.updated cml input swing characteri stics table. 2.updated cdr and cmu jitter performance parameters . 3.updated intrinsic transmit and receive phase nois e performance plots. 4.updated ac/dc electrical characteristics tables. p1.1.0 july 2005 1.revision e silicon: cmos digital 1 .8v power pins p13 and p14 changed to 3.3v. 2.revision e silicon: altfreqsel default clock sele ction changed to 155.52 mhz. revision history r evision # d ate d escription

▲Up To Search▲

Price & Availability of XRT91L800507

	To Download XRT91L800507 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .